Executives

J. Scott Gardner, Chief Executive Officer

J Scott Gardner nwdJ. Scott Gardner, B.S.E.E./MBA is a 25-year veteran of the microprocessor industry. He has held multiple executive positions, with strong emphasis on sales and marketing. Scott was Sr. Director of Developer Ecosystem at AMD from 2013 to 2014, where he directed product management and marketing programs for software aimed at the development community. Previously, Scott was a Sr. Analyst and Sr. Editor for Microprocessor Report from 2009 to 2011.  From 2004 to 2009, he provided consulting and freelance writing services for semiconductor, PC and embedded-system industries.  From 2001 to 2004, Scott was V.P. of Product Strategy for Intrinsity (acquired by Apple), where he helped the company gain broad industry acclaim for its MIPS-based processors. Scott was Director of the Systems Technology Group at IDT in 1999, where he held a number of marketing and executive management roles during his 10 year career. His career spans the industry evolution from a components-driven business into the modern age of system-level solutions for mainstream, consumer-focused technology.

Ronald Foster, Cofounder, Chairman, and Chief Operating Officer

Ron Foster, M.S. Physics, has previously held industry positions at Texas Instruments and Honeywell. His title at Honeywell was Integrated Circuit Design Manager. Mr. Foster subsequently served for several years as Director of Innovation Incubator at the University of Arkansas where he led efforts to encourage technology business startups. From 2006 to 2010 he was co-founder and Chief Operating Officer of Axept, LLC, a startup company focused on MEMS. He brings broad experience in the launch of young technology companies to NanoWatt Design.

Parviz Palangpour, Ph.D., Chief Technology Officer

Parviz Palangpour is an expert in digital logic architectures in general, and asynchronous logic styles in particular. His Ph.D. dissertation focused on Sleep Convention Logic (SCL). His study was concentrated on development of analytical performance models for SCL, as well as CAD tools to support automated conversion of synchronous designs to SCL. His research interests include asynchronous logic design as well as constrained-random and formal verification.